BEST PCIe driver
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response_regs.h
1 /*
2  The response slave port only carries the actual bytes transferred,
3  error, and early termination bits. Reading from the upper most byte
4  of the 2nd register pops the response FIFO. For proper FIFO popping
5  always read the actual bytes transferred followed by the error and early
6  termination bits using 'little endian' accesses. If a big endian
7  master accesses the response slave port make sure that address 0x7 is the
8  last byte lane access as it's the one that pops the reponse FIFO.
9 
10  If you use a pre-fetching descriptor master in front of the dispatcher
11  port then you do not need to access this response slave port.
12 */
13 
14 #ifndef RESPONSE_REGS_H_
15 #define RESPONSE_REGS_H_
16 
17 //#include "io.h"
18 
19 #define RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG (0x0)
20 #define RESPONSE_ERRORS_REG (0x4)
21 
22 // bits making up the "errors" register
23 #define RESPONSE_ERROR_MASK (0xFF)
24 #define RESPONSE_ERROR_OFFSET (0)
25 #define RESPONSE_EARLY_TERMINATION_MASK (1<<8)
26 #define RESPONSE_EARLY_TERMINATION_OFFSET (8)
27 
28 
29 // read macros for each 32 bit register
30 //#define RD_RESPONSE_ACTUAL_BYTES_TRANSFFERED(base) IORD_32DIRECT(base, RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG)
31 //#define RD_RESPONSE_ERRORS_REG(base) IORD_32DIRECT(base, RESPONSE_ERRORS_REG) // this read pops the response FIFO
32 
33 
34 #endif /*RESPONSE_REGS_H_*/